Interactive web site of Télécom ParisTech's ELECINF344/ELECINF381 Robotics and Embedded Systems classes (a.k.a. ROSE, 2012 session).


RoseAce : FPGA

This week I worked on FPGA programming.

I have improve the general architecture :

The calculation block is now more precise : the pre-calculations will not be store in the two external RAM, but, my previous calculation had shown that we can store the pre-calculations on the FPGA RAM. This idea allows the FPGA to access in parallel to the pre-calculations and the pixels store in the external RAM. However, we are just able to store a quarter of pre calculations, the other are calculated thanks to symmetry.

The following blocks are implemented and tested by simulation:

RAM controller, Switch RAM, Fetch pre-calculations, RAM FPGA.

The Fetch pixels block is implemented but not tested yet.

I have begun to implement the gumstix communication block. We have decided to use the following protocol :

We have a 20 bits width address bus between gumstix and FPGA : 18 are used to communicate the address and two to choose the communication mode : 00 : gumstix will write in the external RAM, 01 : gumstix will write in the FPGA RAM, 10 : command mode (to command a RAM switch for example), 11: not use yet.



Jeremy Sauget

Possibly related posts:

  1. RoseAce : FPGA and calcul
  2. RoseAce : general architecture
  3. New architecture, alimentation and PCB
  4. Some calculations to understand our components choice
  5. PCB and RoseAce

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