ELECINF344/381

Interactive web site of Télécom ParisTech's ELECINF344/ELECINF381 Robotics and Embedded Systems classes (a.k.a. ROSE, 2012 session).

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RoseAce : FPGA : calculation flow

Although I had finished implementing the calculation block in the FPGA, a discussion with Alexis changed the general architecture of this block. The choosing architecture is the following :

This architecture is simpler. I will now begin to implement it.

 

 

Jeremy Sauget

Possibly related posts:

  1. RoseAce : FPGA
  2. RoseAce : FPGA and calcul
  3. RoseAce : FPGA programming and simulation
  4. PCB and RoseAce
  5. RoseAce : FPGA programming

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