The FPGA is now able to do a write access with the GPMC (a read access is not possible for the moment). While Sylvain will work on the reading problem (there are some problems with nOE signal … ), I will test some final modules on the FPGA. All modules are written (with the new calculation flow) and, most of them (but not all for the moment) are tested on simulation. Today, I want to test on the FPGA some modules : ram controller and ram switch modules.
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