This video is a little Snake implemented on our device.
To do that, we have stored ten different ranges of pixels in a RAM. (This RAM is a virtual RAM implemented in the FPGA)
Then we displayed alternatively these ranges by reading new addresses in RAM each 0,1s.
Now there are two new step to make; replace the virtual RAM by the real RAM soldered on our PCB and making the pale turn and alternate these ranges no more each period but each position of the blade thanks to the coding wheel.
As our FPGA must communicated with the gumstix using the GPMC bus, 2 clock must be used on the FPGA : GPMC clock for data transfert and, the internal FPGA clock for all the other operations.
To isolate the two clock, we use a dual clock fifo (a altera’s megafunction). Yesterday, Sylvain and I worked all day long trying to make work the fifo (and correcting some problem of simulation … ) in order to turn on LED indicated by the gumstix. It was not a success so, we will keep on working on this problem today.
While I was working on controlling the LED driver, Felix and Sylvain worked on the communication with the gumstix. The news are good :
- the communication between gumstix and FPGA is now working. But, the module for the communication must be modified because, in our real system there will be 2 clock : the FPGA clock and the gumstix clock (just for the data transmission). Felix and Sylvain have finished to implement this new architecture but, it must be tested.
- the control of the LED driver is perfect: we can now turn on all the LED on the propeller, choose the color and the intensity
The next steps are controlling the LED thank to the gumstix and, writing in the external RAM.
The FPGA is now able to do a write access with the GPMC (a read access is not possible for the moment). While Sylvain will work on the reading problem (there are some problems with nOE signal … ), I will test some final modules on the FPGA. All modules are written (with the new calculation flow) and, most of them (but not all for the moment) are tested on simulation. Today, I want to test on the FPGA some modules : ram controller and ram switch modules.