[AmpeROSE] Automating Calibration

Hello, everyone!

One important design issue we must figure out in order to have a complete schematic of AmpeROSE’s is the automatic calibration mechanism. In this post, I will go over the problem definition, and how we arrived at the two solutions we are considering.

A brief recap

Just as a reminder, the current sensing in AmpeROSE will take place on the shunt resistance: a resistance in series with the current path going from VCC to the device under test (DUT), and then to ground. AmpeROSE will work with four measurement ranges, corresponding to four values of the shunt resistance. In order of decreasing shunt values (or equivalently, increasing max. current value of the range).

  • Rshunt = R4 –> (SW1, SW2 and SW3 open)
  • Rshunt = R4 // R3 –> (SW3 closed, SW1 and SW2 open)
  • Rshunt = R4 // R3 // R2 –> (SW2 and SW3 closed, SW1 open)
  • Rshunt = R4 // R3 // R2 // R1 –> (SW1, SW2 and SW3 closed)

(For more details on the ranges and the principles behind this schema, refer to this previous post. )

Let us call the voltage on the shunt “VFILTRE”, the minimum voltage on the shunt before we switch to a lower range “VOFF”, and the maximum voltage on the shunt before we switch to a higher range “VON”. Under this naming scheme, we want to implement the state machine below, where the state is the states of the switches 1 to 3 concatenated, with 1 meaning “closed” and 0 meaning “open”:


While active, AmpeROSE should manipulate the switches in order to transition between the different measurement ranges, according to this state machine. Failing to do so effectively and spending too much time on a wrong calibration has at least two negative consequences:

  • Loss of measurements, as the reading will simply be stuck on the minimal or maximal value of the range.
  • If we have a relatively large values for current and shunt resistance (for instance, a current that should be measured by the small resistance R1 // R2 // R3 // R4 going through R4), a significant voltage drop will develop over the shunt, probably causing the DUT to brown-out.

We considered several possible implementations for this automatic calibration, which are presented below.

Software-based calibration using the external ADC

An apparently natural solution would to be to control the switches with GPIOs coming from the microncontroller, and using the current measurements from our external ADC to guide the controller in calibrating the circuit. However, we have settled on a sampling frequency of 100KHz for the current, and determined the attributes of our external ADC accordingly, opting for a 24 bit SAR ADC working with this sampling rate.

As 1 / (100KHz) = 10us is more than enough  time for a sudden peak in current consumption to damage the measurement, if the resistance is wrong, using our slow but precise external adc won’t do (considering the reaction times of the power supply circuits for the type of DUT we are targeting, we should aim to reach the correct range, which possibly means going from the highest to the lowest one or vice-versa, within 1 to 3 us).

Software-based calibration using the microcontroller’s internal ADC

A variation of the previous idea would be to use the internal ADC of our microcontroller, set to sample the voltage drop on the shunt at a lower precision, but at a higher rate. This measurement would occur in parallel with the one performed by the external ADC, and would be used exclusively to help the microncontroller determine when to change the measurement range.

Due to logistical reasons, we will be using an STM32F767VI instead of a STM32F407ZG as previously discussed. Both microcontrollers feature internal 12-bit ADCs capable of reaching 2.4 millions of samples per second, which could make it possible to perform the three state transitions needed in the worst case within 2us. Furthermore, they feature an analog watchdog mechanism that may be configured to raise an interrupt when the voltage on one of the ADC channels reaches either a minimal or a maximal limit, which would appear to fit like a glove to the automatic calibration.

The problem in this case is the burden that would be applied on the processor. Having to service up to two interrupts related to the calibration every microssecond, which would be detrimental to its other responsibilities, such as managing communications with the user interface or the sd card.

Hardware-based calibration using comparators and feedback loops

The issues with the two concepts above led us to consider hardware-based implementations of the calibration algorithm. We consulted the schematics of the Power Profile Kit marketed by Nordic Semiconductors, and ascertained that it contains such an implementation. The image below is an adaptation of the Power Profiler Kit calibration circuit to our number of measurement ranges. The original version may be consulted by downloading the “Power Profiler Kit Hardware Files” in the “Downloads” tab of and navigating to the third page of the document “PCA63511_Schematic_And_PCB” inside.


The rectangles in the image are LTC6752 ICs, comparators whose output is HIGH when the input voltage V+ is greater than V- and NOT SHDN is HIGH, LOW when V+ is not greater than V- and NOT SHDN is HIGH, and HIGH-Z when NOT SHDN is LOW. The general idea of this asynchronous sequential circuit is to use the feedback on the AND gates to store the state of the calibration state machine, and transition according to the comparators.

Analysing this circuit was fruitful, particularly in terms showing how the LTC6752 could be used, but an options with less components, and simpler to analyse in terms of timing would be preferable, in order to reduce the complexity of the physical implementation on the PCB.

Hardware-based calibration using RS-latches

An alternative with such desirable characteristics would be to use RS-latches to store state, and use only two comparators, such as in the circuit below:


Hardware-based calibration using a bidirectional shift-register

This last option uses a standard component of the 74xx family of digital logic components to implement the calibration state machine.

The functional diagram of the 74HC194 is shown below (source: Its output “Q0 Q1 Q2 Q3” is set asynchronously to 0 when MR is low. Otherwise, it may change at every rising edge of the clock CP, depending on the state of the control inputs S0 and S1:

  • When S0 == 0 and S1 == 0, the output doesn’t change: “Q0(n+1) Q1(n+1) Q2(n+1) Q3(n+1) ” = “Q0(n) Q1(n) Q2(n) Q3(n) ”
  • When S0 == 1 and S1 == 0, the output becomes the result of appending DSR to the left of the original output and taking the leftmost 4 bits: “Q0(n+1) Q1(n+1) Q2(n+1) Q3(n+1) ” = “DSR Q0(n) Q1(n) Q2(n) ”
  • When S0 == 0 and S1 == 1, the output becomes the result of appending DSL to the right of the original output and taking the rightmost 4 bits: “Q0(n+1) Q1(n+1) Q2(n+1) Q3(n+1) ” = “Q1(n) Q2(n) Q3(n) DSL”
  • When S0 == 1 and S1 == 1, the output receives the parallel input: “D0 D1 D2 D3”: “Q0(n+1) Q1(n+1) Q2(n+1) Q3(n+1) ” = “D0(n) D1(n) D2(n) D3(n)

Let us consider what happens when DSL is fixed at HIGH, and DSR at LOW, and S0 and S1 can never be high at the same time. The following state machine is then implemented, with the state written as “Q0 Q1 Q2 Q3”.

We may observe that the state machine within the dotted rectangle is the same one we want to implement for the calibration, it’s just necessary to make the equivalencies:

  • Q3 = switch for R3;
  • Q2 = switch for R2;
  • Q1 = switch for R1;
  • S0 = VFILTRE < VOFF (output of a comparator)
  • S1 = VFILTRE > VON (output of a comparator)

Below, a first version of the connections. A “safe” value is fixed on the parallel input for the case where S0 and S1 are high at the same time, which is not expected to happenn during normal operation of the circuit.

The additional state “1111” has the same effect as “0111”, and can only be reached from it when the comparator indicates VFILTRE > VON, so it shouldn’t be dangerous per se. It does imply, however, that going from “all the switches on” to “all the switches off” may take up to 4 clock cycles. Two possible solutions are to change the equation of S1 to “(VFILTRE > VON) AND NOT Q1”, which requires adding more logic, or to clock the shift register at more than 4MHz.


During initial calibration, the processor must be able to control the switches. directly. If we have GPIO to spare, the following connection gives the processor power to bypass the automatic calibration when necessary and assign whatever values it needs to to the register outputs through the parallel input (it adds two OR gates, though). During normal operation it could set the GPIOs 2 to 5 to the “safe” value.



The two last ideas discussed seem to be the most interesting options at this moment: one is a simplified version of a design implemented by a working product, and other would require very few components. We intend to perform SPICE simulations of versions of our measurement circuit incorporating both options, in order to validate them and decide on our final design.

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