[AmpeROSE] A Tale of Two Calibration Methods

Hello everyone

In the past two weeks, I was involved mainly in simulating the measurement circuit using LTSpice. In previous posts, problems related with switching and amplifying were discussed. In this post, I am going to share the results of the simulation of the calibration method we are going to use.

Brief Recap

In a previous post we discussed the 3 options we had regarding the calibration. Back then, we were considering 4 measurement intervals. Due to the problem with the parasitic capacitance of switches, we decided to use 3 measurement intervals. This will simplify the calibration circuitry because we have to drive only 2 switches.

The basic idea of the calibration logic is the following:

  • If the measured voltage is too small (smaller than a reference OFF voltage) we have to use a shunt resistor with a bigger value and thus turn off the corresponding switch.
  • If the measured voltage is too high (Higher than a reference ON voltage) we have to use a shunt resistor with a smaller value (to avoid high burden voltages) and thus turn on the corresponding switch.

To implement the following logic, 2 methods were considered, simulated and will be discussed in the following

RS Latches

The first circuit we used was based on RS Latches. SW1 is the switch connected to the smallest resistor while SW2 is connected to the resistor of the medium interval.

Then we applied a sine wave at the input of the comparators. Note that in this simulation our goal was to test the logic and thus driving switches will have no impact on the input wave. This was done later when we put the circuit together.

The results of the SPICE simulation are the following

The logic works exactly as needed : When the signal is below OFF reference voltage both switches must be turned off (Note that we are using PMOS transistors). When the signal is above ON reference voltage both switches must be turned on.

However this circuit has a major disadvantage. Since we are using latches, once a switch is turned on/off, the circuit has no time to stabilize the measurements (Switching time – Amplifying …). This will cause the second switch to turn on/off immediately. This is problematic especially for values in the second interval: We will never have stable measurements because we are switching on and off all the time.

Shift Registers

Our second option was using the 74HC194 shift register. We can use this register to implement our calibration state machine. The main advantage of this switch is that time can be controlled using the clock.

We simulated the following circuit

The results – presented in the following picture – are exactly as expected

We were considering using the 74HC194 circuit in our final design because we can easily control the time between switching.

However the major drawback of this circuit is that it does not follow the comparators output instantly. In the worst case scenario, we had a voltage higher than the ON reference voltage right after the clock edge. The burden voltage will increase significantly before we can change the measurement interval.

Going back to RS Latches

We actually have to be able to follow any exceeding fast enough and thus RS latch must be used. However we have to insert a delay in order to give the circuit the time needed to react to these changes.

A simple way to do that is to use RC delay followed by a buffer. The use of a simple buffer will give however a higher delay when SW1 passes from High to Low than when it passes from Low to High. We can then use a comparator with VDD/2. Another method is to use a single component proposed by linear tech LTC6994-2. Note that if we used a simple 74 buffer it would be better to use a RC delay however with the introduction of a comparator, RC has no advantages over the use of a simple single component. That’s why we are going with LTC6994-2.


Another issue we faced was the very fast transition between the lowest possible value (10n) and the highest possible value (300mA) of current. This will introduce a huge burden voltage for a very small amount of time (before the calibration circuit reacts). A decoupling capacitor must be used by the DUT to ensure that we do not have a big voltage drop. This capacitor must be small to not alter our measurements and thus we must guarantee that the drop lasts the minimum possible time.

To do that, we will add a logic that switch directly from the lowest interval to the highest one – without using the intermediate one – in case of a sudden exceeding of the maximal allowed drop voltage. This can be done by comparing the voltage seen by the DUT and the “DUT supply voltage – maximum burden voltage 100mV”.  The output of the comparator will reset both switches instantly. This will not eliminate the voltage drop instantly (as we hoped …) but it would certainly help reducing the time of that drop.

The final calibration circuit we are going to use will look something like

The final results combine the advantages of both circuits: Immediate response with a controlled delay as shown in the following figure

Next Week

In this week we also put last touches to the entire design (for example, we gave the microprocessor direct access to the calibration switches that may be used in the initial calibration or in emergency cases).

FINALLY I am done with LTSpice. Next week my main tasks are related to the PC software that will receive data from our device. I will implement the communication interface and the graph display.

Until next week 🙂

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