[AmpeRose] And yet another problem… Experts… A word…


So, in previous posts, we’ve shown you the results of simulating Switches, initial calibration, automatic calibration sub-system, etc. In addition, we’ve talked about some problems and how we’ve approached them and shared the results with you. However, we are still having a little problem, let’s see what’s happening… The origin of the problem is the DUT itself, to be more precise, it’s the decoupling capacitors that are bothering us. Yesterday, we showed you (In this post) that  a decoupling capacitor must be used by the DUT to ensure that we do not have a big voltage drop in case of a very fast transition between current ranges. This guarantees that the DUT will always be powered up.

Now, we’re getting closer to the problem.

Problem Statement

A negative current is being fed to AmpeRose by the decoupling capacitors during fast current transitions, therefore delaying the stabilisation of the op amp output.

Remember that we’re sampling each 10 us. That being said, a lot of samples would need to be discarded (~ 70) before voltage stabilization.

What do we want?

We want to block the current flowing from the decoupling capacitor of the DUT, easy, let’s use a diode.

Not that easy! In fact, an ideal diode would have definitely solved our problem(?), because it allows the current to flow in one direction only and does not consume any voltage (drop voltage = 0). However, such a diode does not exist… 🙁

Different solutions

Constructors (Linear tech, Maxim,…) provide different near-ideal diode solutions. However, the drop voltage is still huge, and therefore not suitable for our needs.

Well, I hope I made the problem clear… If you have any questions or clarification requests, we’re here to answer… And, it goes without saying… We’re open for any and all suggestions.

Thank you.

[AmpeROSE] Current generation for the initial calibration


As you saw in a previous post, we are going to do some measurements on the AmpeROSE to do an initial calibration, to correct eventual imprecisions. To do that we need to be able to put a current that we know and control precisely. In order to achieve our goal, we decided to use a current mirror, the one we are going to use was built by Analog Devices and has the reference ADL5315. The following figure shows you how we will use it.

Since it is a current mirror there is some current being copied from somewhere to somewhere. Here it is the current flowing through INPT that is copied to IOUT. Then this current is injected in our measurement system : MIR+ and MIR- are connected to the shunts.

To generate a current on INPT, we used a resistor to force the current which depends on the voltage on the INPT pin. So, we also need to control the voltage on this pin. That is simple here because we have the same voltage on INPT and VSET, so we only need to force one voltage on the VSET pin to have the same on INPT. Then we know the voltage and the resistor so we can deduce the current. In our application, we want to have some precise current, so we chose the current and then we compute and apply the voltage  we need of VSET.  As you can see, we have 2 resistors, so depending the current we need to generate, we use one or both (which is almost equivalent as saying the other here).

To control the voltage on VSET, we are using a voltage divider. This voltage divider is built upon a digital potentiometer. So, we can use it to vary  the VSET voltage to generate multiple values of currents.

Here are the equations that allow us to know how to generate a current :

  • VSET= Rpot /(Rpot + 100K)
  • Iout=Iin= VSET/Rinpt

According to these equation these are the values of current we can generate : from 100nA to 500nA and from 500uA to 2.5mA.

[AmpeROSE] A Tale of Two Calibration Methods

Hello everyone

In the past two weeks, I was involved mainly in simulating the measurement circuit using LTSpice. In previous posts, problems related with switching and amplifying were discussed. In this post, I am going to share the results of the simulation of the calibration method we are going to use.

Brief Recap

In a previous post we discussed the 3 options we had regarding the calibration. Back then, we were considering 4 measurement intervals. Due to the problem with the parasitic capacitance of switches, we decided to use 3 measurement intervals. This will simplify the calibration circuitry because we have to drive only 2 switches.

The basic idea of the calibration logic is the following:

  • If the measured voltage is too small (smaller than a reference OFF voltage) we have to use a shunt resistor with a bigger value and thus turn off the corresponding switch.
  • If the measured voltage is too high (Higher than a reference ON voltage) we have to use a shunt resistor with a smaller value (to avoid high burden voltages) and thus turn on the corresponding switch.

To implement the following logic, 2 methods were considered, simulated and will be discussed in the following

RS Latches

The first circuit we used was based on RS Latches. SW1 is the switch connected to the smallest resistor while SW2 is connected to the resistor of the medium interval.

Then we applied a sine wave at the input of the comparators. Note that in this simulation our goal was to test the logic and thus driving switches will have no impact on the input wave. This was done later when we put the circuit together.

The results of the SPICE simulation are the following

The logic works exactly as needed : When the signal is below OFF reference voltage both switches must be turned off (Note that we are using PMOS transistors). When the signal is above ON reference voltage both switches must be turned on.

However this circuit has a major disadvantage. Since we are using latches, once a switch is turned on/off, the circuit has no time to stabilize the measurements (Switching time – Amplifying …). This will cause the second switch to turn on/off immediately. This is problematic especially for values in the second interval: We will never have stable measurements because we are switching on and off all the time.

Shift Registers

Our second option was using the 74HC194 shift register. We can use this register to implement our calibration state machine. The main advantage of this switch is that time can be controlled using the clock.

We simulated the following circuit

The results – presented in the following picture – are exactly as expected

We were considering using the 74HC194 circuit in our final design because we can easily control the time between switching.

However the major drawback of this circuit is that it does not follow the comparators output instantly. In the worst case scenario, we had a voltage higher than the ON reference voltage right after the clock edge. The burden voltage will increase significantly before we can change the measurement interval.

Going back to RS Latches

We actually have to be able to follow any exceeding fast enough and thus RS latch must be used. However we have to insert a delay in order to give the circuit the time needed to react to these changes.

A simple way to do that is to use RC delay followed by a buffer. The use of a simple buffer will give however a higher delay when SW1 passes from High to Low than when it passes from Low to High. We can then use a comparator with VDD/2. Another method is to use a single component proposed by linear tech LTC6994-2. Note that if we used a simple 74 buffer it would be better to use a RC delay however with the introduction of a comparator, RC has no advantages over the use of a simple single component. That’s why we are going with LTC6994-2.


Another issue we faced was the very fast transition between the lowest possible value (10n) and the highest possible value (300mA) of current. This will introduce a huge burden voltage for a very small amount of time (before the calibration circuit reacts). A decoupling capacitor must be used by the DUT to ensure that we do not have a big voltage drop. This capacitor must be small to not alter our measurements and thus we must guarantee that the drop lasts the minimum possible time.

To do that, we will add a logic that switch directly from the lowest interval to the highest one – without using the intermediate one – in case of a sudden exceeding of the maximal allowed drop voltage. This can be done by comparing the voltage seen by the DUT and the “DUT supply voltage – maximum burden voltage 100mV”.  The output of the comparator will reset both switches instantly. This will not eliminate the voltage drop instantly (as we hoped …) but it would certainly help reducing the time of that drop.

The final calibration circuit we are going to use will look something like

The final results combine the advantages of both circuits: Immediate response with a controlled delay as shown in the following figure

Next Week

In this week we also put last touches to the entire design (for example, we gave the microprocessor direct access to the calibration switches that may be used in the initial calibration or in emergency cases).

FINALLY I am done with LTSpice. Next week my main tasks are related to the PC software that will receive data from our device. I will implement the communication interface and the graph display.

Until next week 🙂

[AmpeRose] GUI Skeleton

Hello AmpeRose fans,

This post is a bit overdue… Well a lot overdue, I was supposed to write it last week :p

So, that week, in addition to working on the calibration schema, I created the class diagram for our graphic interface, which I ordered into three well wrapped levels:

  • Back-end
  • Data View
  • Graphic interface


The Back-end handles communications with AmpeRose, which includes

  • Reading Data sent by AmpeRose
  • Decoding data using a specific configuration (Translation)
  • Sending commands to AmpeRose
  • Performing special operations with the data (save to file, backup, send to database…)

N.B: Just yesterday, we decided that we might add another class that would handle error correction, using correction info sent forth by AmpeRose. (Benefits of being late :p)



The Data View does not handle the data per Se, but it handles how this data will be viewed.

For instance, it is here that we can choose to view the data as a simple continuous stream, or as lapses that obey to a certain trigger. It is also here that we can calculate the FFT of our data points, to allow the user to see the frequency spectrum of his device. The data container of the Data View will act as a moving window for the measurements, i.e. it will contain a fixed number of points (10^7 to 10^8), and as new data pours in, values will be replaced.


The graphic interface

This part of the pc software is what the user will see and use directly. It will view the data in a useful manner, and will allow for control over AmpeRose, as well as the other components of the software.


That’s all for tonight folks,

But stay tuned for the way more interesting post about the updates on our calibration circuit this week!

P.S: Some titles are links to images of the class diagrams.

[AmpeRose] Believe it or not, STM32CubeMX wasn’t able to find a solution at full speed clock, but guess what, I did it…

Good evening everyone,

This week, I worked on schematics, simulation and power supply.

I started by reviewing the configuration of the STM32F767 microprocessor that is going to be used in our project. I used the STM32CubeMX software to review the pin assignments, check for potential conflicts.

In addition, one of the important aspect of this software is the clock configuration. Manually configuring it wouldn’t be an easy task though.

However, it’s not always possible to find an automatic solution using this software because there are a lot of constraints to take into consideration, lucky me, that was the case.

Eventually, I managed to manually configure the clock at full speed (spoiler 216MHz 🙂 ) and respect all different constraints. Yes I did it and I hate STM32CubeMX for that :).

In terms of schematics, I also reviewed them:  finalized the configuration of the microprocessor, removed some the unused pull down resistors in the ethernet schema in order to use less components and simplify the routing.

To have an idea of our full consumption, thus designing the right decoupling capacitors, I compiled a list that specifies the consumption of each component. The list is not fully complete yet because there has been some changes in some components, so I will finalize it when we choose the appropriate components that suit our needs.

Also, during this week, I joined the team and did some simulations in order to try to minimize the full drop voltage that occurs during the 100ns that corresponds more or less to the op amp response time. After all, the solution was to design an suitable decoupling capacitor that will maintain the voltage across the DUT.

Stay stuned,

See you next week.

[AmpeROSE] The amplification

As you saw in our previous posts, we were going to use the amplifier MAX4239 but after some simulations, we decided to replace it with the ADA4807. We will explain here why we took this decision.

To test the amplifier, we did a simulation using them in the same way they will be used in AmpeROSE: as a differential amplifier with a gain of 100. Here is the schematic of this simulation.

As you can see, we put the same signal as input on the two differential amplifiers, this signal is represented on the following figure.

It is a simple pulse, we put this signal because we think it represents well the activation of a peripheral that consumes a lot after the system was in sleep mode. When we tried such an input on our simulation with the MAX4239, we got a really bad surprise that you can see on the following picture:

The amplifier did not react fast enough because it has a slew rate too low! After that we decided that we have to change it because a common case like this one should be measured well.

So we searched for others operational amplifiers with a better slew rate and we finally choose to use the ADA4807 which was much better as you can see on the output on the figure below.

You know now why we change our amplifier. This choice has unfortunately some drawbacks, notably we will need here a negative supply. This amplifier also has bigger offset but since the software will correct it with the initial calibration, this is not a problem.

[AmpeROSE] – Pining for a PCB

Hello, everyone!

We’ve been really focused on making sure the physical circuit for AmpeROSE is the best it can be, as it is, in many ways, the most delicate part of our project. In this post, I’d like to talk about how our microcontroller will interact with the rest of our custom printed circuit board, some preliminary planning we’ve done on the firmware, and some interesting interactions between these two tasks.

The Firmware

We have decided to use the ChibiOS real-time operating system to support our embedded code, as we are already familiar with it, and it offers what we need in terms of device drivers and RTOS features (threads, synchronization primitives, etc.) . Our application code will be organized around three main threads, corresponding to the three main tasks performed by AmpeROSE:

  • A data acquisition thread which receives measurements through an interrupt-driven process, detailed further along in this post, applies any necessary signal processing and logical decisions (such as discarding the measurement immediately after a change in measurement) and passes it along to the transmission thread.
  • A transmission thread responsible for sending the measurements to the user interface through Ethernet or USB, or to the SD card through SDIO.
  • A command reception thread responsible for receiving commands from the user interface and controlling the whole program to follow them.

AmpeROSE’s Microcontroller

As you may remember from a previous post, we’ll now be using a STM32F767VIT6 as our microcontroller (or μC). It comes in a low-profile quad flat packaging (LQFP), with 100 pins to interface with the rest of the circuit. You can see its dimensions in milimeters on this image from page 54 of the datasheet.

Of the 100 pins, 16 are reserved for connecting the μC to various voltages (VSS, VDD, VDDA, VCAP…), one is a reset pin and one is used to tell the μC which boot address to use between two programmed options. The 82 other pins may either be used as general-purpose input/output or set to perform a number of alternate functions, the particular subset of alternate functions available being specific to each pin. These pins represent our “budget” for connecting the STM32F767 to the different peripherals on the board, including the current measurement circuit.

Below, the impact of the different peripherals we plan to include in AmpeROSE on this “budget” is discussed:


The STM32F767 includes a 10/100 MAC controller, which must be connected to an external ethernet transceiver (which implements the physical layer of communications). We’ll be using a LAN8742A connected to the μC through a Reduced Media-Independent Interface (RMII). Compared to the standard MII, RMII uses 9 signals instead of 18, but works at a clock frequency of 50MHz instead of 25MHz, which means we have to be particularly careful with the signal integrity of these connections. For each of the 9 RMII signals, only one pin of our μC is capable of performing its function, so we did not have much choice on this matter.

SD Card

The STM32F767 includes two interfaces for exchanging data with SD cards, but one of them conflicts (= needs some of the same pins) with the Ethernet, so we’ll be using the other one on a 4-data pins configuration (which means 6 pins are used, 4 for data + one for clock and one for commands).


The STM32F767 includes two USB interfaces: one for Full-Speed usb connections, for which a transceiver is also included in the packaging, and one for High-Speed connections. In order to use the High-Speed connection, it would be necessary to have an external transceiver, but some of the 12 (!) pins that must be used for connecting the transceiver to the μC are already taken by the Ethernet, so we’ll be working at Full Speed. As AmpeROSE will only ever operate as a USB device, there’s no need to use the ID usb signal, so only two pins (for the DM and DP signals) are needed.


We’ll be using a 32.7Hz quartz and a 20MHz quartz to provide clock sources for the μC, so the 4 pins that may be configured as connections for such oscillators will be used for this.

Context Bits

Six pins will be inputs for receiving context signals from the device under test, through a connector.


After performing a set of SPICE simulations, we have finally settled on an automatic calibration scheme, which will be detailed on another post (spoiler for those following at home: it will be a modified version of the circuit with RS latches). The simulations have also led us to reduce the number of measurement ranges we’ll be working with from 4 to 3, which means that we’ll have only two switches determining which resistors the current from the device under test will go through.

To survey the state of the control signals going from the automatic calibration circuit to these two switches (and thus, the state of the calibration), two pins will be used as inputs. It would be desirable that the μC keeps track of the state of the calibration whenever it changes, rather than just sampling it when a new measurement is made, to avoid the risk of doing this sampling right during a transition and ending with a spurious value.

Our strategy for doing so is to configure the two pins as interrupt sources, which will be activated at rising or falling edges of their input signals. In our μC, the GPIO pins with names ending with numbers from 5 to 9 all activate the same IRQ, as do the pins with names ending with numbers 10 to 15 . We will connect the calibration outputs to two pins in the first group (5 to 9), and use the common IRQ callback for the group to read the state of the pins and update a variable in memory with them.

Additionally, a mechanism for the processor to preempt the automatic calibration and assume direct control of the switches is also needed for our initial calibration process. The schema below, which ties up another 3 pins, appears to be the best solution:

The initial calibration also makes it necessary to have an output pin for controlling whether the shunt resistance receives current from the device under test or from our current mirror.

Finally, as we’ll have a mechanism for the processor to control the switches directly, our supervisors have instructed us the leave open the possibility of doing the calibration through software. This implies that the processor must have a way of knowing when the voltage on the shunt has reached a lower or upper limit and must be changed. Two options for doing so are using the internal adc for reading the voltage output by our amplification stage (needs 1 pin) and reading the outputs from the two comparators of the calibration circuit (needs 2 pins). We have enough free pins for doing either, or even both, strategies.


In order to control the potentiometers present in the circuit, a 2-wire I2C interface will be used.

Analog-to-Digital Converter

We’ve chosen the AD7766 as our external ADC. The protocol for reading data from it is identical to SPI, so one of the SPI interfaces from μC will be connected to it. As this connection will only ever transmit data from the slave (the ADC) to the master (the μC), and contains a single slave, only two SPI signals are needed: CLK and MISO.

Two further signals are needed: one is a GPIO input configured as an interrupt source, connected to the DREADY pin of the ADC, which goes low when there is a new measurement to be read. The other is a 1.024 MHz clock output from a channel of one of the μC timers, which will serve as the master clock for the ADC, determining its sampling rate. In conclusion, 4 pins will be used for this interface.

In the firmware, two callbacks will be used to take care of communications with the ADC:

  • One called for the interrupt launched when the DRDY pin goes low. It will start the reading of the measurements through SPI. It will also read the current state of the context inputs from the DUT, and of the calibration from memory, and place them on a chibiOS mailbox.
  • One called when the SPI transmission ends: it will concatenate the 24-bit measurement bits with the 6 bits received from the previous callback through the mailbox, and send them through another mailbox to the data acquisition thread.

In Conclusion

Taking all the interfaces discussed in this post, we have 44 pins left unassigned.


[AmpeRose] Switching…

Hello, everyone!

In this post, I’m going to talk about the switches and the problems encountered and most importantly, how we approached these problems.

The switches are used to switch between different ranges. By acting on the switches, the value of the equivalent resistance changes, so the range changes as well.

Switches – problems

The simulation under LTspice takes into account the real model of the components thus making it possible to study the behavior of the system and to anticipate possible problems.

Ideal model In order to switch between the ranges, PMOS transistors are used.

VG = VCC => passing state

VG = GND => blocking state. 

In order to test the real behavior of the transistors, we consider the following schema:

For an ideal model we obtain the following results:

The results are in line with the expected values.

Simulated transistors

Among the transistors that have been simulated:

  • DMG3415U
  • DMP2035U
  • BSS84

In the following, we will see the results of the simulation of the first transistor, DMG3415U. This transistor has an ON resistance of 42.5mΩ and a leakage current of 1nA (for a temperature 25C).

Although the overshoot and undershoot can be accepted (very short duration), the real problem is that, after the undershoot, we never arrive at the expected value.  And this behavior is really catastrophic, since the voltage at the input of the ADC will not be the expected value.

In order to fully understand the cause of the problem, we embarked on an in-depth research into the mosfet transistor model.

A deeper look inside Mosfet Transistor

Let’s consider the following simplified model of a mosfet transistor:

RDS(on) – On Resistance T

This is the total resistance between the drain and source in a mosfet transistor. RDS(on) is the basis for a maximum current rating of the MOSFET and is also associated with current loss. So RDS(on) is not zero, therefore, it must be taken into consideration because a big resistance causes huge problems with respect to the lowest shunt resistor (~mOhm). Thus, the lower RDS(on), the better.

Intrinsic capacitances

Cgs, Cgd and Cds are the intrinsic capacitances. They are unwanted capacitances, but still are part of the transistor. Together with the resistance in the circuit, they put an upper limit to the speed of the transistor.

Ciss, Input Capacitance

This is the input capacitance measured between the gate and source terminals with the drain shorted to the source for AC signals.

Ciss = C gs + Cgd

The input capacitance must be charged to the threshold voltage before the device begins to turn on, and discharged to the plateau voltage before the device turns off. Therefore, the impedance of the drive circuitry and Ciss have a direct effect on the turn on and turn off delays.

Coss – Output Capacitance

This is the output capacitance measured between the drain and source terminals with the gate shorted to the source for AC voltages.

Coss = Cds +Cgd.

For soft switching applications, Coss is important because it can affect the resonance of the circuit.

Crss – Reverse Transfer Capacitance

This is the reverse transfer capacitance measured between the drain and gate terminals with the source connected to ground.

Crss = Cgd.

The reverse transfer capacitance, often referred to as the Miller capacitance, is one of the major parameters affecting voltage rise and fall times during switching. It also affects the turn-off delay time.

Miller effect in a nutshell

The Miller effect is a special case of the Miller theorem when the impedance element (connected between the amp’s input and output) is a capacitor.

This effect leads to an increase in the input capacitance.The consequence is slowing down the transition and increasing the propagation delay time.

Spurious oscillation

MOSFETs are capable of switching large amounts of current in incredibly short times. Their inputs are also relatively high impedance, which can lead to stability problems. Under certain conditions high voltage MOSFET devices can oscillate at very high frequencies due to stray inductance and capacitance in the surrounding circuit.


The connections with the circuit exhibit a parasitic inductance, which is in no way specific to the MOSFET technology, but has important effects because of the high commutation speeds. Parasitic inductances tend to maintain their current constant and generate overvoltage during the transistor turn off, resulting in increasing commutation losses.

A parasitic inductance can be associated with each terminal of the MOSFET. They have different effects:

  • the gate inductance and the input capacitance of the transistor can constitute an oscillator. This must be avoided as it results in very high commutation losses (up to the destruction of the device)
  • the drain inductance tends to reduce the drain voltage when the MOSFET turns on, so it reduces turn on losses. However, as it creates an overvoltage during turn-off, it increases turn-off losses.
  • the source parasitic inductance has the same behaviour as the drain inductance, plus a feedback effect that makes commutation last longer, thus increasing commutation losses.


In conclusion, it is the intrinsic parasitic capacitances that come into play when measuring low current.

Switches – solutions

We saw that several parameters come into play when we want to select a mosfet transistor, this choice of course, depends on the type of application. The manufacturer provides in its datasheet, the values ​​of the various parameters:

  • RD (on)
  • Ciss
  • Coss
  • Crss
  • I leakage
  • 6 …

We  want a transistor with weak resistance, current leakage and capacitance. However, it was impossible to find such a transistor which met all these parameters.

Here is a compiled list of the most interesting transistors we’ve found:

  • DMG3415U
  • DMP2035U
  • BSS84
  • RRQ030P03
  • NextPowerS3
  • CSD25501F3

The solution to this problem is not to find the transistor having a minimum parasitic capacitance (although it would be very useful) because it is insufficient.

Several solutions were considered:

  • Using Load Switches (ADG801)
  • Configuration Change (Shunt resistors in series and the transistor will be in parallel)

The most realistic solution is therefore to try to manipulate the parameter R (in τ = RC) and not only the parameter C.

Current range

In the previous posts, it has already been established that there will be 4 current ranges, here is a quick recap:

  • 739 µA    →    303 mA
  • 7.39 µA   →    3,03 mA
  • 73.9 nA   →    30,3 µA
  • 1 nA        →    303 nA

The fourth range is not part of the AmpeRose specification, since the latter is designed to measure very low currents of the order of a few hundred nA which correspond well to the consumption of some embedded systems operating in standby mode.

Therefore, the current range was updated as follows:

  • 100uA − 300mA
  • 1uA     − 3mA
  • 10nA   − 30uA

Note that by reducing the number of ranges (4 -> 3), we also reduce the value of the largest resistance, therefore, improve the response after closing the switch.

[AmpeROSE] Initial Calibration

Good evening everyone!

In this long overdue post I will talk a little bit about one of the two main subjects I have worked on these past two weeks: The calibration method.

In a perfect world the whole initial calibration method would not be needed, but we live in the real world, so here goes…


We have gone to great lengths to get the components most suitable for our purposes. That said, the components of our measurement circuits are far from perfect: they present a number of errors we have to tend to.


These are the most important errors that must be corrected if we are to obtain meaningful results from AmpeROSE:

  1. Shunt errors:
    1. Precision error on Shunt resistor values
    2. Added resistance of the switch transistor with each Shunt resistor
    3. Leakage current of said transistors when blocking
    4. Input bias current of the buffers after the Shunt stage
  2. Amplification errors:
    1. Gain error of the operational amplifier in use
    2. Offset voltage of said amplifier


1.4. AKA the input bias current of the buffers is negligible. Note that we added the buffers to reduce this leak current, which was before that of the Op Amp.


Now for the calibration method. Our calibration will run as iterations of a 2-step process:

  1. Consider the Shunts perfect and calibrate the Amplification stage
  2. Consider the Amplification stage perfect and calibrate the Shunts

For step 1, we will apply a zero voltage difference on the input of the Op Amp, but we will get a non-zero output. this is a static error, the amplified input offset voltage of the Op Amp. We will measure this value, using our ADC, and save it. We will the apply very specific non-zero inputs to the amplification stage. From each output we get, we subtract the static error. in the end, we approximate the slope of the output line. (Of course we will take care not to saturate the Op Amp.) Now, also through software, we can correct values we get from the amplifier.

Now for step 2, we will use a current sink (discussed in a different post) to force a very specific, and well known current to pass through each Shunt branch. And… You guessed it… We will not measure the value we’re supposed to measure, due to the errors discussed above. Then we use these values to shift our measurement scales, in the software.

We will repeat these steps until we reach a fixed point. This calibration may also be performed when AmpeROSE heats up, because component characteristics change with heat. Also, non-linear errors are a nuisance we will have to endure.

So, to wrap this up, you might have noticed that we’re gonna need some extra components to be able to accomplish these calibrations. Thankfully those will not affect the measures themselves… We’re going to add a current sink to our circuit, as well as switches to cut it clean from the Supply of the DUT.

[AmpeROSE] Automating Calibration

Hello, everyone!

One important design issue we must figure out in order to have a complete schematic of AmpeROSE’s is the automatic calibration mechanism. In this post, I will go over the problem definition, and how we arrived at the two solutions we are considering.

A brief recap

Just as a reminder, the current sensing in AmpeROSE will take place on the shunt resistance: a resistance in series with the current path going from VCC to the device under test (DUT), and then to ground. AmpeROSE will work with four measurement ranges, corresponding to four values of the shunt resistance. In order of decreasing shunt values (or equivalently, increasing max. current value of the range).

  • Rshunt = R4 –> (SW1, SW2 and SW3 open)
  • Rshunt = R4 // R3 –> (SW3 closed, SW1 and SW2 open)
  • Rshunt = R4 // R3 // R2 –> (SW2 and SW3 closed, SW1 open)
  • Rshunt = R4 // R3 // R2 // R1 –> (SW1, SW2 and SW3 closed)

(For more details on the ranges and the principles behind this schema, refer to this previous post. )

Let us call the voltage on the shunt “VFILTRE”, the minimum voltage on the shunt before we switch to a lower range “VOFF”, and the maximum voltage on the shunt before we switch to a higher range “VON”. Under this naming scheme, we want to implement the state machine below, where the state is the states of the switches 1 to 3 concatenated, with 1 meaning “closed” and 0 meaning “open”:


While active, AmpeROSE should manipulate the switches in order to transition between the different measurement ranges, according to this state machine. Failing to do so effectively and spending too much time on a wrong calibration has at least two negative consequences:

  • Loss of measurements, as the reading will simply be stuck on the minimal or maximal value of the range.
  • If we have a relatively large values for current and shunt resistance (for instance, a current that should be measured by the small resistance R1 // R2 // R3 // R4 going through R4), a significant voltage drop will develop over the shunt, probably causing the DUT to brown-out.

We considered several possible implementations for this automatic calibration, which are presented below.

Software-based calibration using the external ADC

An apparently natural solution would to be to control the switches with GPIOs coming from the microncontroller, and using the current measurements from our external ADC to guide the controller in calibrating the circuit. However, we have settled on a sampling frequency of 100KHz for the current, and determined the attributes of our external ADC accordingly, opting for a 24 bit SAR ADC working with this sampling rate.

As 1 / (100KHz) = 10us is more than enough  time for a sudden peak in current consumption to damage the measurement, if the resistance is wrong, using our slow but precise external adc won’t do (considering the reaction times of the power supply circuits for the type of DUT we are targeting, we should aim to reach the correct range, which possibly means going from the highest to the lowest one or vice-versa, within 1 to 3 us).

Software-based calibration using the microcontroller’s internal ADC

A variation of the previous idea would be to use the internal ADC of our microcontroller, set to sample the voltage drop on the shunt at a lower precision, but at a higher rate. This measurement would occur in parallel with the one performed by the external ADC, and would be used exclusively to help the microncontroller determine when to change the measurement range.

Due to logistical reasons, we will be using an STM32F767VI instead of a STM32F407ZG as previously discussed. Both microcontrollers feature internal 12-bit ADCs capable of reaching 2.4 millions of samples per second, which could make it possible to perform the three state transitions needed in the worst case within 2us. Furthermore, they feature an analog watchdog mechanism that may be configured to raise an interrupt when the voltage on one of the ADC channels reaches either a minimal or a maximal limit, which would appear to fit like a glove to the automatic calibration.

The problem in this case is the burden that would be applied on the processor. Having to service up to two interrupts related to the calibration every microssecond, which would be detrimental to its other responsibilities, such as managing communications with the user interface or the sd card.

Hardware-based calibration using comparators and feedback loops

The issues with the two concepts above led us to consider hardware-based implementations of the calibration algorithm. We consulted the schematics of the Power Profile Kit marketed by Nordic Semiconductors, and ascertained that it contains such an implementation. The image below is an adaptation of the Power Profiler Kit calibration circuit to our number of measurement ranges. The original version may be consulted by downloading the “Power Profiler Kit Hardware Files” in the “Downloads” tab of and navigating to the third page of the document “PCA63511_Schematic_And_PCB” inside.


The rectangles in the image are LTC6752 ICs, comparators whose output is HIGH when the input voltage V+ is greater than V- and NOT SHDN is HIGH, LOW when V+ is not greater than V- and NOT SHDN is HIGH, and HIGH-Z when NOT SHDN is LOW. The general idea of this asynchronous sequential circuit is to use the feedback on the AND gates to store the state of the calibration state machine, and transition according to the comparators.

Analysing this circuit was fruitful, particularly in terms showing how the LTC6752 could be used, but an options with less components, and simpler to analyse in terms of timing would be preferable, in order to reduce the complexity of the physical implementation on the PCB.

Hardware-based calibration using RS-latches

An alternative with such desirable characteristics would be to use RS-latches to store state, and use only two comparators, such as in the circuit below:


Hardware-based calibration using a bidirectional shift-register

This last option uses a standard component of the 74xx family of digital logic components to implement the calibration state machine.

The functional diagram of the 74HC194 is shown below (source: Its output “Q0 Q1 Q2 Q3” is set asynchronously to 0 when MR is low. Otherwise, it may change at every rising edge of the clock CP, depending on the state of the control inputs S0 and S1:

  • When S0 == 0 and S1 == 0, the output doesn’t change: “Q0(n+1) Q1(n+1) Q2(n+1) Q3(n+1) ” = “Q0(n) Q1(n) Q2(n) Q3(n) ”
  • When S0 == 1 and S1 == 0, the output becomes the result of appending DSR to the left of the original output and taking the leftmost 4 bits: “Q0(n+1) Q1(n+1) Q2(n+1) Q3(n+1) ” = “DSR Q0(n) Q1(n) Q2(n) ”
  • When S0 == 0 and S1 == 1, the output becomes the result of appending DSL to the right of the original output and taking the rightmost 4 bits: “Q0(n+1) Q1(n+1) Q2(n+1) Q3(n+1) ” = “Q1(n) Q2(n) Q3(n) DSL”
  • When S0 == 1 and S1 == 1, the output receives the parallel input: “D0 D1 D2 D3”: “Q0(n+1) Q1(n+1) Q2(n+1) Q3(n+1) ” = “D0(n) D1(n) D2(n) D3(n)

Let us consider what happens when DSL is fixed at HIGH, and DSR at LOW, and S0 and S1 can never be high at the same time. The following state machine is then implemented, with the state written as “Q0 Q1 Q2 Q3”.

We may observe that the state machine within the dotted rectangle is the same one we want to implement for the calibration, it’s just necessary to make the equivalencies:

  • Q3 = switch for R3;
  • Q2 = switch for R2;
  • Q1 = switch for R1;
  • S0 = VFILTRE < VOFF (output of a comparator)
  • S1 = VFILTRE > VON (output of a comparator)

Below, a first version of the connections. A “safe” value is fixed on the parallel input for the case where S0 and S1 are high at the same time, which is not expected to happenn during normal operation of the circuit.

The additional state “1111” has the same effect as “0111”, and can only be reached from it when the comparator indicates VFILTRE > VON, so it shouldn’t be dangerous per se. It does imply, however, that going from “all the switches on” to “all the switches off” may take up to 4 clock cycles. Two possible solutions are to change the equation of S1 to “(VFILTRE > VON) AND NOT Q1”, which requires adding more logic, or to clock the shift register at more than 4MHz.


During initial calibration, the processor must be able to control the switches. directly. If we have GPIO to spare, the following connection gives the processor power to bypass the automatic calibration when necessary and assign whatever values it needs to to the register outputs through the parallel input (it adds two OR gates, though). During normal operation it could set the GPIOs 2 to 5 to the “safe” value.



The two last ideas discussed seem to be the most interesting options at this moment: one is a simplified version of a design implemented by a working product, and other would require very few components. We intend to perform SPICE simulations of versions of our measurement circuit incorporating both options, in order to validate them and decide on our final design.