[AmpeROSE] Recalibrating our Architecture

Hello, everyone!

In this post, I’d like to discuss a final significant change that our architecture for AmpeROSE underwent in the end of December.

The calibration problem

As you may recall, a fundamental task for AmpeROSE is to perform “automatic calibration”, controlling in real time the value of its shunt resistance, which is used to convert the current drawn by the device under test (DUT) into a tension that is amplified and measured by an ADC. Each possible value for the shunt corresponds to a range of current values that may be effectively measured with it. Having an inadequate shunt value at a given time can cause the following negative consequences:

  1. If the current is too small for the shunt (there’s a larger available value for the shunt that we should be using), we lose precision.
  2. If the current is too big for the shunt (there’s a smaller available value for the shunt that we should be using), we lose measurements, as the reading will just be stuck at the maximum value for the measurement range corresponding to the current shunt. More importantly, we risk having a brownout on the DUT if the burden voltage becomes large and the situation persists for longer than the DUT’s power supply circuit can handle.

You may consult these two previous posts (1, 2) to review our process for arriving at the automatic calibration scheme we initially based our schematics and PCB design on. Here is a high-level view of it, with the calibration circuit in the center:

In this configuration, hardware comparators are used to generate signals that indicate whenever the amplified shunt voltage has surpassed the upper limit for the current measurement range (VIN>VON), or gone below its lower limit (VIN<VOFF). A third comparator determines whether the burden voltage (voltage on the shunts) has surpassed its maximum allowable value, its output being ALERT. These outputs are fed into a circuit composed of discrete ICS (NAND and NOT gates, SR latches and delay blocks) that implements the calibration logic and generated two outputs (SW1 and SW2) which contror transistor switches which may be used to connect and disconnect resistor in parallel with the shunt, thus changing its value.

In this configuration, it is the microcontoller’s job to read each mesurement from the ADC when it’s ready, through SPI, and sample values of the calibration outputs and of the context bits to associate with the measurement. It also determines the reference voltages for the comparators using its digital to analog converters and controlling a potentiometer.

In the course of the elaboration of our printed circuit board (PCB), this approach for the calibration circuit proved to be problematic, in particular the placing and routing of the different ICs, some of them containing several logic gates that would , not to mention the difficulty of reasoning about the timing of the logic signals. More importantly, the calibration logic would be locked into what is determined by the discrete ICs placed on the PCB, and would be impossible to correct if tests with the finished PCB revealed that corrections would be in order.

In view of these issues, our supervisors encouraged us to consider two alternative approaches that would grant us more flexibility and could be implemented more expediently:

Calibrate using a FPGA

This approach uses a small field-programmable gate array – FPGA (small in terms of package size/pin numbers, and in terms of number of interal logic cells) to implement the calibration logic and generate the SWx outputs. The calibration circuit would be described using a hardware description language such as SystemVerilog, which we have employed often in our embedded systems education, and could be corrected by reprogramming the FPGA through JTAG.

Additionally, we envision using the fpga to read the ADC measurement and the context bits, and prepare and transmit the complete measurement word to the microcontroller though SPI.

Calibrate using the microcontroller

In this approach the outputs of the comparators would be connected to microcontroller pins and would generate fast interrupts, whose service routines would implement the calibration logic and update the shunt control signals.

This design has the advantage of simplifying even more the PCB, and would take advantage of the relatively powerful microcontroller we’re using in our design. On the other hand, performing the calibration does represents a significant burden on microntroller if compared with the circuit with the FPGA, especially because it will also be managing an Ethernet connection.

And the winner is…

Neither! I mean, both! Our PCB will contain a MAX3000A fpga with 44 pins and 64 macrocells, but the components have been placed and routed in such a way that it will be possible to implement either of the designs present above in the PCB, just by reprogramming the microcontroller and the FPGA. The calibration using the FPGA will work essentially as described previously, while for the calibration using the microcontroller, the FPGA will be programmed to simply transmit signals transperantly between the microcontroller and other components in the board.

This strategy will allow us to evaluate the feasibility of both strategies, with the goal of determining which would be more interesting for a more mature version of AmpeROSE. I’m currently working on the SystemVerilog code for the calibration using FPGA, which should then be simulated and tested so we can be confident it’s likely to work when we receive our PCB.

[AmpeROSE] A Tale of Two Calibration Methods

Hello everyone

In the past two weeks, I was involved mainly in simulating the measurement circuit using LTSpice. In previous posts, problems related with switching and amplifying were discussed. In this post, I am going to share the results of the simulation of the calibration method we are going to use.

Brief Recap

In a previous post we discussed the 3 options we had regarding the calibration. Back then, we were considering 4 measurement intervals. Due to the problem with the parasitic capacitance of switches, we decided to use 3 measurement intervals. This will simplify the calibration circuitry because we have to drive only 2 switches.

The basic idea of the calibration logic is the following:

  • If the measured voltage is too small (smaller than a reference OFF voltage) we have to use a shunt resistor with a bigger value and thus turn off the corresponding switch.
  • If the measured voltage is too high (Higher than a reference ON voltage) we have to use a shunt resistor with a smaller value (to avoid high burden voltages) and thus turn on the corresponding switch.

To implement the following logic, 2 methods were considered, simulated and will be discussed in the following

RS Latches

The first circuit we used was based on RS Latches. SW1 is the switch connected to the smallest resistor while SW2 is connected to the resistor of the medium interval.

Then we applied a sine wave at the input of the comparators. Note that in this simulation our goal was to test the logic and thus driving switches will have no impact on the input wave. This was done later when we put the circuit together.

The results of the SPICE simulation are the following

The logic works exactly as needed : When the signal is below OFF reference voltage both switches must be turned off (Note that we are using PMOS transistors). When the signal is above ON reference voltage both switches must be turned on.

However this circuit has a major disadvantage. Since we are using latches, once a switch is turned on/off, the circuit has no time to stabilize the measurements (Switching time – Amplifying …). This will cause the second switch to turn on/off immediately. This is problematic especially for values in the second interval: We will never have stable measurements because we are switching on and off all the time.

Shift Registers

Our second option was using the 74HC194 shift register. We can use this register to implement our calibration state machine. The main advantage of this switch is that time can be controlled using the clock.

We simulated the following circuit

The results – presented in the following picture – are exactly as expected

We were considering using the 74HC194 circuit in our final design because we can easily control the time between switching.

However the major drawback of this circuit is that it does not follow the comparators output instantly. In the worst case scenario, we had a voltage higher than the ON reference voltage right after the clock edge. The burden voltage will increase significantly before we can change the measurement interval.

Going back to RS Latches

We actually have to be able to follow any exceeding fast enough and thus RS latch must be used. However we have to insert a delay in order to give the circuit the time needed to react to these changes.

A simple way to do that is to use RC delay followed by a buffer. The use of a simple buffer will give however a higher delay when SW1 passes from High to Low than when it passes from Low to High. We can then use a comparator with VDD/2. Another method is to use a single component proposed by linear tech LTC6994-2. Note that if we used a simple 74 buffer it would be better to use a RC delay however with the introduction of a comparator, RC has no advantages over the use of a simple single component. That’s why we are going with LTC6994-2.


Another issue we faced was the very fast transition between the lowest possible value (10n) and the highest possible value (300mA) of current. This will introduce a huge burden voltage for a very small amount of time (before the calibration circuit reacts). A decoupling capacitor must be used by the DUT to ensure that we do not have a big voltage drop. This capacitor must be small to not alter our measurements and thus we must guarantee that the drop lasts the minimum possible time.

To do that, we will add a logic that switch directly from the lowest interval to the highest one – without using the intermediate one – in case of a sudden exceeding of the maximal allowed drop voltage. This can be done by comparing the voltage seen by the DUT and the “DUT supply voltage – maximum burden voltage 100mV”.  The output of the comparator will reset both switches instantly. This will not eliminate the voltage drop instantly (as we hoped …) but it would certainly help reducing the time of that drop.

The final calibration circuit we are going to use will look something like

The final results combine the advantages of both circuits: Immediate response with a controlled delay as shown in the following figure

Next Week

In this week we also put last touches to the entire design (for example, we gave the microprocessor direct access to the calibration switches that may be used in the initial calibration or in emergency cases).

FINALLY I am done with LTSpice. Next week my main tasks are related to the PC software that will receive data from our device. I will implement the communication interface and the graph display.

Until next week 🙂