I started writing the code for the FPGA module which will be feeding the LED drivers. It corresponds to the “LED Driver driver” from our FPGA architecture diagram. In order to have a functional system as soon as possible once we receive the PCB I am also building a test bench to test the module. So far I have assertions on the timing requirements (hold times, setup times, etc.), the validity of the output data and on the internal state machine coherence. I will first finish the test bench and then the module.
Concerning the timing requirements, there are 7 different LAT commands. The datasheet of the TLC5957 indicates the setup time before a rising edge of SCLK for 6 of them. However, there is a diagram of the application note of the driver (Figure 7 of SLVUAF0) suggesting that there is also a setup time to respect for the 7th command. Does anyone from spirose have additional information on that?