FPGA architecture, episode 2

The architecture of the FPGA has evolved since the last post.

General architecture

First, since we don’t plan on controlling the rotation speed from the HPS anymore, this feature has been removed from the architecture.

Moreover, the SCLK and GCLK are now generated by each of the 20 LED band controllers since we have enough ouput pins on the FPGA. This results in a simpler design and better signal integrity on these two signals.

Each LED band controller controls a LED driver. More information on the way this driver works can be found on this post.

For the inner memory of the LED band controller we use a dual port, dual clock synchronous RAM, which is proposed in Intel’s recommended HDL coding style for memory inference.

The AXI slave takes the data sent by the AXI master and writes in the memory, which contains a cylinder of pixels.

The FC setter module sets (as its name implies) the FC data latch of the driver after the reset. This register stores the configuration of the driver. The wanted FC value is hard-coded as a parameter in the FC setter, since we have no interest in using different modes. While the FC is being set, FC_en is high.

The output multiplexer is a purely combinatory element. It selects the output to be sent to the driver:

  • If FC_en is high, the FC_SIN and FC_LAT signals are selected
  • If FC_en is low, SIN takes the value rdata[bit] and LAT takes the value GS_LAT (GS stands for Grey Scale)

When the FC setter is not active, the driver controller deduces from the current angle and the multiplexing signal the address in the memory of the data that needs to be sent to the LED driver. This data is available one cycle later to the output multiplexer. It also generates the bit signal that selects which bit of this data needs to be sent, as well as the LAT signal necessary to control the driver.

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