Since the last episode, a lot of drastic changes occur in the FPGA architecture.
Those three signals are now generated by the SYNC module. This reduces the number of GCLK, LAT and GCLK sent outside the FPGA. They will be duplicated thanks to clock buffers on the “highway” PCB.
We decided to realize this change to reduce the number of pins used, this will make the main PCB easier to route. Moreover, to ensure proper functioning, the 20 Led band controllers had to send the same SCLK and GCLK and to send all the data for the following LEDs when the previous ones are displayed. This is why we also decided to generate SCLK, LAT and GCLK from the Sync module. It will make easier the synchronization between led band controllers.
The HPS will be used to control the framerate of LitSpin. It will periodically send this signal to led band controllers to tell them to display the new image. This signal tells them to change the display buffer and to display it immediately even if the previous image is not completely displayed. The remaining buffer will be written by the DMAC.
This signal is used to reset led band controllers.
We decided to use a DMA Controller IP directly on the FPGA. We will not use the DMAC integrated into the HPS because it is more complex to use and we did not totally understand how it can be controlled.
Every time the HPS sends a new_image signal, it will, in parallel, order to the DMAC to copy the image in the RAM into the 20 led band controllers. Because we use an Altera IP, the data buses are Avalon buses. This was also one of the reasons we use DMAC IP. Indeed, an Avalon slave is really easier to implement than an AXI3 Slave.
To prevent issues in the display due to the DMA transfer, we decided to put 2 buffers per led band controllers. One will be displayed while the other one will receive data from the DMAC.
Moreover, we decided to only use 8-bits per colour. However, the led driver takes a minimum of 9 bits per colour. So, we will add a 0 as LSB in the data sent to the driver