In this post, I detailed a new version of the global architecture. In this one, I will detail the V1 of the led band controller architecture.
This version is fully implemented and FC Setter, Multiplexer and Memory submodules were successfully tested.
However, during a small meeting with Alexis, he explained there is a problem in our architecture. Indeed, every submodule is synchronized with SCLK even if it is not completely a clock (this “clock” can be switched off). However, the angle signal is not synchronized with it but with the FPGA clock. So we have two clock domains which can lead to issues. So, we will create a new version that will be synchronized with the FPGA clock.
Moreover, Alexis asked us to add two features:
- The possibility to change the FC config from the HPS by adding a port on the FC Setter
- The possibility to set the SOUT from the GS controller directly from the HPS