Make Led Band Controller Great Again

I finished programming the Led Band Controller and its testbench.

Test realized

I realized different kinds of test:

  • Writing test only: this test is here to confirm we can write correctly in both buffers. This test writes random values in the RAM.
  • Read test only: this test is here to confirm we can read correctly in both buffers. This test reads 1000 random bits in the RAM.
  • Writing and reading test: This test is here to confirm we can read and write at the same time in the RAM. Each buffer is written with random values while the other one receives 768 random access.
  • HPS SOUT test: This test is here to confirm the HPS can write on the SOUT channel.

Each test has been passed successfully.

Difficulties encountered for the testbench

I encountered several difficulties during testbench implementation. For instance, the propagation time is not taken into account. So I encountered some misbehaviors like very tiny peaks, like Dirac pics.

for (i = 0; i<1000; i++) begin
    color = colors_rand[i];
    angle = angle_rand[i];
    row   = row_rand[i];
    bits  = bits_rand[i];

    @(posedge clk);
    @(negedge clk);

    assert ((bits==0 & SOUT == 0) | (SOUT == data[r_addr/16][r_addr%16][bits-1])) 
    else   begin 
            success = 0;
            if (bits == 0)
                $error("Data reading test failed with index: %d, row: %d, angle: %d, color: %d and bit: %d.\nexpected: %h\nvalue  : %h", i, row, angle, color, bits, 0, SOUT);
            else
                $error("Data reading test failed with index: %d, row: %d, angle: %d, color: %d and bit: %d.\nexpected: %h\nvalue  : %h", i, row, angle, color, bits, data[r_addr/16][r_addr%16][bits[2:0]], SOUT);
            end

end

In the above code, I had to add the @(negedge clk) instruction to prevent those peaks. Moreover, without it, some test cases were false whereas they were true because the test of equality arrives just after the positive edge of the clock and the memory writes the r_data at the same moment. This is why I also add this @(negedge clk), to be sure the r_data is sent before the test.

I encountered other problems like this one. They were fixed with the same method.

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