Reality Is Often Disappointing


I realized a synthesizable top module to test the Sync module and Led Band Controller together. The goal of this top module is to simulate the ticks sent by the Hall effect and the optical fork sensors. But also to send data to the Leb Band Controller to simulate the DMA Controller. In the output, one can read SCLK, GCLK, LAT, SOUT, row_en[3:0] (multiplexing), turn_tick, n_rst.

With @nathan-claudel, we decided to synthesize and test it on the DE1-SOC. The output signals are exited on the GPIO1. Then I used a Saleae device to probe the signals.

DE1-SoC and Saleae probe

Problems detected

Problems of the top module

First, we have to fix several issues due to the implementation of the top module. Indeed, we didn’t use every signal, as the signals from the HPS but I didn’t set them to 0. So those signals were interfering with the useful ones.

Problems with the Sync module

With @nathan-claudel, we found an error in the implementation of the LAT generator. There was an extra LATGS. This was a consequence of an issue on the bit_sel signal which sent the bit 9 whereas the index of the bits are between 0 and 8.


Now we will complete our test benches to check if data sent by the Led Band Controller are the good ones. This is the toughest part, so we wanted to be sure the other parts are good to test this one.

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