Today, Sibille and I tested the common reference time sharing between Phyllos. After coding the whole part, it worked pretty well and we managed to communicate with three Phyllos and the main_stm almost on our first try.
What was just a bit more challenging was when we tried to make the current time master (see yesterday’s post) disappear so that a new one could be reelected.
We needed to make sure that we could propagate the time tops from the master chosen among the bottom PCBs, through the main PCB and up until the main STM32. This point was a quick success.
Another, and more challenging point, was to insure robustness in the choice of the time master. The particularly interesting point is when the current master disappears, every Phyllo tries to become master at the same time. There are two problematic consequences.
First, whichever new master is elected, it will start numbering the tops back to zero which will be strange for the client side (STM32 of the main board). Second, all the remaining Phyllos will simultaneously try to become a master.
The second issue is only about coding and we solved it today. For the first one however, we decided that we could afford to accept such a temporary confusion so we simply let it be.
Here is a diagram representing the test we have made :
It had required some logistic because we couldn’t find any USB hub, but with a lot of cables and good faith and several computers, we finally received some synchronized top_messages while listening on the UART bus of the two ESP32 :
As we can see, the top is delivered to the STM32 with great synchronization. As a reminder, we hope for a precision on the top of 10ms.
We also have a thread transmitting the “TOP” to the main board STM32 via UART upon receipt of a time_top message.
One more detail about time_top messages : each message contains a uint8_t representing the time index. The main board keeps a table with 256 cases updated by storing in
case[time_index] the OS time count when the time_top message containing time_index is received. In case some time_top messages are missed, the corresponding cases are set to 0.
We will use this table to synchronize several Phyllos. Roughly, a Phyllo will send an animation offer to another Phyllo, proposing to start the animation with a given ID at a given delay after time_top<x> is received. If the receiving Phyllo isn’t busy (already sharing an animation or playing an animation on its own), it checks if it has a correct time_top<x> reference (the corresponding case in the table doesn’t contain 0) and accepts or rejects the proposition accordingly. We will work on this protocol very soon and keep you posted 🙂
At the end of today, we came across a very disconcerting bug. To provide you with the captures from the analyser above, we had to use two main_esp and we decided to have them both on my computer, one on
/dev/ttyUSB0 and the other on
/dev/ttyUSB1. However, we soon discovered that whereas the one on
/dev/ttyUSB0 worked exactly as expected, the other one kept rebooting with a
LoadProhibited error. We tried switching the ESP32, the USB cable, the USB port, the computer, the Phyllo id (the only difference between the two codes flashed was the id attributed) but the constant was that
/dev/ttyUSB1 did not ever work while
/dev/ttyUSB0 did not ever not work.
If you have any lead, please advise us 🙂
Stay tuned !