A first look at the FPGA architecture

In order to synchronize the LEDs and create a persistence of vision image, we use a CycloneV SOC.

Here is a first idea of the architecture we might use :

The ARM processor fills a buffer with the next image to be displayed, that is then swapped with the second buffer. It can pull this image from the SD card, or from another source such as the text printing function we plan on adding.

The full buffer is then accessed by a Direct Memory Access (DMA) IP that then sends the relevant cylinder (32 * 128 pixels) to each LED band controller that is then stored in their memory.

The sync module uses the signal from the hall effect sensor to compute the current rotation speed and deduce the approximate angular position of the rotating part(current_angle).

This current_angle combined with the pcb_angle parameter (that gives the angular position of the PCB in the configuration) allows each LED band controller to read a in the relevant addresses of their memory and flash the LEDs with the color corresponding to their position.

This first draft gives us an idea of the architecture we are going to use, however a lot of choices have still to be made, such as the type of buses to use.

3 Replies to “A first look at the FPGA architecture”

    1. For the moment, we considered using Quartus.
      It is closed-source but we have already used it and it is available at school.

      However we stay open to new propositions. I will take a look at Symbiotic EDA too see if it works with our platform.

      1. I’d advise against trying Yosys’ experimental features during ROSE. Synthesis support for CycloneV FPGAs is still experimental, as far as I can see, and FPGAs are already tricky enough without trying experimental software (especially since you don’t have a lot of time). Yosys also doesn’t fully support SystemVerilog. On the other hand, I’m looking forward to checking it out with a Lattice FPGA one day.

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