Another Brick in the Wall

I recently built the first version of the LitSpin Linux but also the MCVEVK Linux if we need it. I first tested the MCVEVK version and it worked perfectly. However, when I tried with the LitSpin one, I had some trouble: the MCV didn’t boot anymore or nothing was sent on the UART which is also a problem.

RTFM!

To recover the SOM I tried to follow the different steps given by ARIES. The first problem was to get the Recovery Sof which is not available online. So, I sent ARIES an email to ask for it. They send me back the recovery file 20 minutes after.… Read more

Build your own Linux for LitSpin

Today, I will teach you how to bake a Linux for your LitSpin project

Requirements needed

  • A tested Linux distribution (list). For this recipe, Ubuntu 19.10 seems to work even if it is not tested
  • A lot of packages. Here the list depending on your distribution

Tools needed

Clone those repositories in the same working directory

Creation of the meta-litspin layer

With the different tools, we can build a Linux distribution for the MCV evaluation kit (MCVEVK) and the MCV development board (MCVEVP).… Read more

There can only be one SD card in town

On the Aries MCV, the MMC pins of the HPS are already used to control the MMC flash. However, we need an SD card. So, we decided to add a µSD card on the SPI1 interface because SD cards can be controlled in SPI. So, I added the µSD card to the SPI1 interface like this:

&spi1 {
	status = "okay";
	clock-frequency = <100000000>;

	mmc-slot@0 {
		reg = <0>;
		compatible = "mmc-spi-slot";
		spi-max-frequency = <50000000>;
		voltage-ranges = <3300 3300>;
	};
	
};

Before testing on the MCV, we realize tests on the DE1-SoC. Something to notice, we already built the Linux kernel for the DE1-SoC and it booted correctly without the SD card on the SPI interface.… Read more

#TeamTrees

With Nathan, we work a lot on the creation of the Linux distribution. On my side, I am working on how to add an sd card on an SPI bus and Nathan is working on the driver for the USB WiFi Dongle.

Device tree

An SD card can not be detected and set automatically like a USB device. We have to tell Linux there is a micro SD host on an SPI bus. We have to put a micro SD host on an SPI bus because the eMMC bus is already taken by the Flash. To tell Linux, there is a micro SD host on the SPI bus, the simplest method is to add it in the device tree blob.… Read more

Alea Yocto est

We need to build the disk image for the MCV SoM. To do this we have two options given by Aries, the SoM manufacturer. We can use Buildroot or Yocto.

Yocto

We decided to test Yocto first. Tarik Graba advised us to use it and a previous group who works with the same SoM used it too.

This project is a cross-compilation framework based on recipes. Every recipe contains a list of dependencies and a set of instructions (like a real recipe). The interesting point is the sources needed in a recipe can be directly downloaded online. So if some dependencies are missing, they will be automatically downloaded.… Read more

Reality Is Often Disappointing

Installation

I realized a synthesizable top module to test the Sync module and Led Band Controller together. The goal of this top module is to simulate the ticks sent by the Hall effect and the optical fork sensors. But also to send data to the Leb Band Controller to simulate the DMA Controller. In the output, one can read SCLK, GCLK, LAT, SOUT, row_en[3:0] (multiplexing), turn_tick, n_rst.

With @nathan-claudel, we decided to synthesize and test it on the DE1-SOC. The output signals are exited on the GPIO1. Then I used a Saleae device to probe the signals.

DE1-SoC and Saleae probe

Problems detected

Problems of the top module

First, we have to fix several issues due to the implementation of the top module.… Read more

QsIssues

After having tested the implementation of the Led Band Controller. I decided to create an IP on QSys. However, we had some problems with that.

Localparam issue

The first problem is a consequence of the use of local parameters. Every interface signals which depend on a local parameter have a length of -1 like angle for instance:

parameter NB_ANGLES = 128;
localparam ANGLE_WIDTH =   $clog2(NB_ANGLES);
input wire [ANGLE_WIDTH - 1:0] angle;

So I would like to know if someone knows how to deal with this problem.

hps_io conduit issue

This problem is a smaller one and has a way to fix it but it is not very clean.… Read more

Make Led Band Controller Great Again

I finished programming the Led Band Controller and its testbench.

Test realized

I realized different kinds of test:

  • Writing test only: this test is here to confirm we can write correctly in both buffers. This test writes random values in the RAM.
  • Read test only: this test is here to confirm we can read correctly in both buffers. This test reads 1000 random bits in the RAM.
  • Writing and reading test: This test is here to confirm we can read and write at the same time in the RAM. Each buffer is written with random values while the other one receives 768 random access.
Read more

New implementation

I implemented the new version of the led band controller by following the new architecture explained in this post. This version is simpler than the previous one. With the new version, a huge part of the computing is inside the Synchronisation module.

Small problem with the angle

We split a turn into 128 parts. However, we have 20 PCBs and 20 doesn’t divide 128. 128/20 = 6.4. So we decided to take the nearest integer for the ANGLE_PCB parameter of the Led Band Controller. The worst case is a difference of 0.4. This represents a difference of 1.125° and that represents for the outermost PCB a gap of 1.8mm… Read more

Led Band Controller new architecture

In this post, I detailed a new version of the global architecture. In this one, I will detail the V1 of the led band controller architecture.

Led band controller architecture

This version is fully implemented and FC Setter, Multiplexer and Memory submodules were successfully tested.

However, during a small meeting with Alexis, he explained there is a problem in our architecture. Indeed, every submodule is synchronized with SCLK even if it is not completely a clock (this “clock” can be switched off). However, the angle signal is not synchronized with it but with the FPGA clock. So we have two clock domains which can lead to issues.… Read more