The architecture of the FPGA has evolved since the last post.
First, since we don’t plan on controlling the rotation speed from the HPS anymore, this feature has been removed from the architecture.
Moreover, the SCLK and GCLK are now generated by each of the 20 LED band controllers since we have enough ouput pins on the FPGA. This results in a simpler design and better signal integrity on these two signals.
Each LED band controller controls a LED driver. More information on the way this driver works can be found on this post.
For the inner memory of the LED band controller we use a dual port, dual clock synchronous RAM, which is proposed in Intel’s recommended HDL coding style for memory inference.… Read more