FPGA architecture, episode 2

The architecture of the FPGA has evolved since the last post.

General architecture

First, since we don’t plan on controlling the rotation speed from the HPS anymore, this feature has been removed from the architecture.

Moreover, the SCLK and GCLK are now generated by each of the 20 LED band controllers since we have enough ouput pins on the FPGA. This results in a simpler design and better signal integrity on these two signals.

Each LED band controller controls a LED driver. More information on the way this driver works can be found on this post.

For the inner memory of the LED band controller we use a dual port, dual clock synchronous RAM, which is proposed in Intel’s recommended HDL coding style for memory inference.… Read more

A first look at the FPGA architecture

In order to synchronize the LEDs and create a persistence of vision image, we use a CycloneV SOC.

Here is a first idea of the architecture we might use :

The ARM processor fills a buffer with the next image to be displayed, that is then swapped with the second buffer. It can pull this image from the SD card, or from another source such as the text printing function we plan on adding.

The full buffer is then accessed by a Direct Memory Access (DMA) IP that then sends the relevant cylinder (32 * 128 pixels) to each LED band controller that is then stored in their memory.… Read more