Synchronization update

Today with Nathan we spent a lot of time rethinking the work distribution between the synchronizer and the led band controller. I won’t go into details because Nathan already explained it in his last post, but basically the synchronizer will have more work than expected because it will have to generate all the signals needed by the led band controller to output the right bit at the right time. Indeed since every led band has the same display pattern (the leds are all multiplexed the same way on the PCBs), the calculations can be made only once for each led band.… Read more

Let that sync in

After a number of interrocations on the FPGA architecture, we are back to the drawing board.

Indeed, Alexis pointed out that our previous design created a lot of redundancy in the led band controllers. The computation of the current controlled leds, of the current controlled colors and even of the current written bit can be mutualized between each LED band.

That’s why from now on, our synchronization module will have more duties. It will generate :

  • the SCLK and LAT signals (see this post about the LED driver)
  • the current angle
  • the row, color and bit to be sent at any moment

But what does the led band controller do, then?… Read more

Led Band Controller new architecture

In this post, I detailed a new version of the global architecture. In this one, I will detail the V1 of the led band controller architecture.

Led band controller architecture

This version is fully implemented and FC Setter, Multiplexer and Memory submodules were successfully tested.

However, during a small meeting with Alexis, he explained there is a problem in our architecture. Indeed, every submodule is synchronized with SCLK even if it is not completely a clock (this “clock” can be switched off). However, the angle signal is not synchronized with it but with the FPGA clock. So we have two clock domains which can lead to issues.… Read more

V1: Led Band Controller

First organization

I implemented the first version of the led band controller. We divide this controller into 4 submodules:

  • FC Setter: This submodule is used to set the driver FC register
  • Mux: This submodule takes the current led, color, angle, and multiplexing and returns the corresponding address
  • Memory: This submodule represents the double buffer of the controller
  • GS controller: This submodule is used to set the SOUT signal

TODO

We have to test this first implementation thanks to a testbench. Firstly, we will test each submodule independently. The FC Setter has been already successfully tested.

FPGA architecture, the end of the trilogy (it maybe is a prelogy we don’t know)

In an FPGA far far away

Since the last episode, a lot of drastic changes occur in the FPGA architecture.

The new global architecture

SCLK, LAT and GCLK

Those three signals are now generated by the SYNC module. This reduces the number of GCLK, LAT and GCLK sent outside the FPGA. They will be duplicated thanks to clock buffers on the “highway” PCB.

We decided to realize this change to reduce the number of pins used, this will make the main PCB easier to route. Moreover, to ensure proper functioning, the 20 Led band controllers had to send the same SCLK and GCLK and to send all the data for the following LEDs when the previous ones are displayed.… Read more

FPGA architecture, episode 2

The architecture of the FPGA has evolved since the last post.

General architecture

First, since we don’t plan on controlling the rotation speed from the HPS anymore, this feature has been removed from the architecture.

Moreover, the SCLK and GCLK are now generated by each of the 20 LED band controllers since we have enough ouput pins on the FPGA. This results in a simpler design and better signal integrity on these two signals.

Each LED band controller controls a LED driver. More information on the way this driver works can be found on this post.

For the inner memory of the LED band controller we use a dual port, dual clock synchronous RAM, which is proposed in Intel’s recommended HDL coding style for memory inference.… Read more

A first look at the FPGA architecture

In order to synchronize the LEDs and create a persistence of vision image, we use a CycloneV SOC.

Here is a first idea of the architecture we might use :

The ARM processor fills a buffer with the next image to be displayed, that is then swapped with the second buffer. It can pull this image from the SD card, or from another source such as the text printing function we plan on adding.

The full buffer is then accessed by a Direct Memory Access (DMA) IP that then sends the relevant cylinder (32 * 128 pixels) to each LED band controller that is then stored in their memory.… Read more