Reality Is Often Disappointing

Installation

I realized a synthesizable top module to test the Sync module and Led Band Controller together. The goal of this top module is to simulate the ticks sent by the Hall effect and the optical fork sensors. But also to send data to the Leb Band Controller to simulate the DMA Controller. In the output, one can read SCLK, GCLK, LAT, SOUT, row_en[3:0] (multiplexing), turn_tick, n_rst.

With @nathan-claudel, we decided to synthesize and test it on the DE1-SOC. The output signals are exited on the GPIO1. Then I used a Saleae device to probe the signals.

DE1-SoC and Saleae probe

Problems detected

Problems of the top module

First, we have to fix several issues due to the implementation of the top module.… Read more

Make Led Band Controller Great Again

I finished programming the Led Band Controller and its testbench.

Test realized

I realized different kinds of test:

  • Writing test only: this test is here to confirm we can write correctly in both buffers. This test writes random values in the RAM.
  • Read test only: this test is here to confirm we can read correctly in both buffers. This test reads 1000 random bits in the RAM.
  • Writing and reading test: This test is here to confirm we can read and write at the same time in the RAM. Each buffer is written with random values while the other one receives 768 random access.
Read more

New implementation

I implemented the new version of the led band controller by following the new architecture explained in this post. This version is simpler than the previous one. With the new version, a huge part of the computing is inside the Synchronisation module.

Small problem with the angle

We split a turn into 128 parts. However, we have 20 PCBs and 20 doesn’t divide 128. 128/20 = 6.4. So we decided to take the nearest integer for the ANGLE_PCB parameter of the Led Band Controller. The worst case is a difference of 0.4. This represents a difference of 1.125° and that represents for the outermost PCB a gap of 1.8mm… Read more

Led Band Controller new architecture

In this post, I detailed a new version of the global architecture. In this one, I will detail the V1 of the led band controller architecture.

Led band controller architecture

This version is fully implemented and FC Setter, Multiplexer and Memory submodules were successfully tested.

However, during a small meeting with Alexis, he explained there is a problem in our architecture. Indeed, every submodule is synchronized with SCLK even if it is not completely a clock (this “clock” can be switched off). However, the angle signal is not synchronized with it but with the FPGA clock. So we have two clock domains which can lead to issues.… Read more

V1: Led Band Controller

First organization

I implemented the first version of the led band controller. We divide this controller into 4 submodules:

  • FC Setter: This submodule is used to set the driver FC register
  • Mux: This submodule takes the current led, color, angle, and multiplexing and returns the corresponding address
  • Memory: This submodule represents the double buffer of the controller
  • GS controller: This submodule is used to set the SOUT signal

TODO

We have to test this first implementation thanks to a testbench. Firstly, we will test each submodule independently. The FC Setter has been already successfully tested.