I realized a synthesizable top module to test the Sync module and Led Band Controller together. The goal of this top module is to simulate the ticks sent by the Hall effect and the optical fork sensors. But also to send data to the Leb Band Controller to simulate the DMA Controller. In the output, one can read SCLK, GCLK, LAT, SOUT, row_en[3:0] (multiplexing), turn_tick, n_rst.
With @nathan-claudel, we decided to synthesize and test it on the DE1-SOC. The output signals are exited on the GPIO1. Then I used a Saleae device to probe the signals.
Problems of the top module
First, we have to fix several issues due to the implementation of the top module.… Read more
I implemented the new version of the led band controller by following the new architecture explained in this post. This version is simpler than the previous one. With the new version, a huge part of the computing is inside the Synchronisation module.
Small problem with the angle
We split a turn into 128 parts. However, we have 20 PCBs and 20 doesn’t divide 128. 128/20 = 6.4. So we decided to take the nearest integer for the ANGLE_PCB parameter of the Led Band Controller. The worst case is a difference of 0.4. This represents a difference of 1.125° and that represents for the outermost PCB a gap of 1.8mm… Read more
In this post, I detailed a new version of the global architecture. In this one, I will detail the V1 of the led band controller architecture.
This version is fully implemented and FC Setter, Multiplexer and Memory submodules were successfully tested.
However, during a small meeting with Alexis, he explained there is a problem in our architecture. Indeed, every submodule is synchronized with SCLK even if it is not completely a clock (this “clock” can be switched off). However, the angle signal is not synchronized with it but with the FPGA clock. So we have two clock domains which can lead to issues.… Read more